Binary Rate Multiplier using PIC Configurable Logic Block

This article explains how to implement a high-speed 6-Bit asynchronous Binary Rate Multiplier (BRM) using the PIC16F13145 Microcontroller’s built-in Configurable Logic Block (CLB). Enabling efficient hardware-based frequency scaling for applications such as digital waveform synthesis, precision pulse generation, and time-domain signal modulation. Examples of BRMs can be found in the TTL and CMOS families (74LS97 and CD4089 devices). The PIC16F’s CLB can be easily configured to replicate or replace the functionality of these devices.

A relatively little-known but historically significant circuit is the Binary Rate Multiplier (BRM). First introduced in the late 1940s, the BRM was an innovative tool used primarily for serial multiplication and other arithmetic operations in early electronic systems. At a time when digital computers were still in their infancy and prohibitively expensive, the BRM provided a practical means to perform high-speed mathematical calculations using binary logic. It functioned by modulating the frequency of a pulse stream in proportion to a binary input value, effectively multiplying a base rate by a binary-coded number. These circuits were particularly useful in analogue-to-digital conversion systems, early data transmission, and control applications. The BRM remained in use throughout the 1950s and 1960s, especially in specialized military, aerospace, and scientific instrumentation. However, with the advent and mass production of affordable digital computers and microprocessors in the 1970s, the use of BRMs declined significantly, as software-based solutions offered greater flexibility and ease of implementation.

The name Binary Rate Multiplier can be somewhat misleading, as it suggests an increase in frequency, whereas in practice, a BRM always produces an output frequency that is less than or equal to its input frequency. A BRM operates by selectively gating input clock pulses based on a binary control word, effectively scaling down the frequency according to a specified ratio.

The schematic diagram here shows the gating logic section of a 4-bit BRM, which functions by dividing the input clock frequency by a factor of N/16, where N is a 4-bit binary number ranging from 0 to 15. This means the output frequency is directly proportional to the binary value of N. For example, if N = 7 and the input clock frequency (CLKIN) is 1.6 MHz, then the output frequency (CLKOUT) will be (7/16) × 1.6 MHz = 700 kHz.

The circuit works by allowing exactly N pulses out of every 16 input pulses to pass through to the output, creating a form of pulse-density modulation. When N = 0, no output pulses are generated, and when N = 15, nearly all but one pulse in every 16 are passed through, resulting in an output frequency close to the input frequency but still slightly lower.

A synchronizing output (SYNCOUT) is also provided for timing and triggering purposes. It generates a single, fixed-width pulse once every input clock cycle group, typically once every 16 input pulses in a 4-bit BRM, regardless of the value of N. The SYNCOUT pulse corresponds to the same position in the cycle as the output would occur when N = 1, serving as a reliable timing reference for external circuits to align or synchronize with the BRM’s internal cycle.

To complete the functionality of the Binary Rate Multiplier (BRM), a 4-bit binary counter is employed to generate sequential timing signals that divide the input clock (CLKIN) into progressively slower signals: CLKIN/2, CLKIN/4, CLKIN/8, and CLKIN/16. These divided clock phases serve as timing references for the BRM’s logic, determining which input pulses are passed to the output based on the value of the binary control word N. For high-speed applications, it is critical to use a synchronous binary counter, in which all flip-flops are triggered simultaneously by the same clock edge. This synchronous operation significantly reduces cascading propagation delays and minimizes pulse skew, which are common issues in asynchronous (ripple) counters where each flip-flop triggers the next. The schematic diagram shown illustrates such a counter built using JK flip-flops configured to toggle, and NAND gates to control the enable conditions of the next stage. This configuration ensures reliable, high-speed performance and precise timing alignment between the counter outputs and the gating logic of the BRM.

In this section, we will explore the practical steps for using the MPLAB Code Configurator (MCC) Configurable Logic Block (CLB) Synthesizer to implement the counter and logic necessary for both 4-bit and 6-bit Binary Rate Multipliers (BRMs). The 4-bit BRM configuration enables fractional frequency division by N/16, where N ranges from 1 to 15, while the extended 6-bit BRM supports division by N/64, where N ranges from 1 to 63. These configurations allow the output frequency to be finely scaled between 1/16 and 15/16 or 1/64 and 63/64 of the input frequency, depending on the resolution selected. Such control is ideal for applications requiring digital waveform synthesis, precise timing control, or pulse density modulation. The implementation involves constructing a synchronous counter (6-bit) and logic gates that compare the counter output to the programmed value of N, gating the input clock accordingly. The MCC CLB Synthesizer rationalizes this process by providing a graphical interface to configure LUTs, counters, and combinatorial logic, and allows assignment of internal signals to GPIO output pins for external integration and debugging.

The Configurable Logic Block (CLB) module within the PIC16F13145 microcontroller offers a versatile and compact alternative to traditional CPLD or FPGA devices for implementing custom digital logic. With its array of programmable Look-Up Tables (LUTs), logic gates, flip-flops, and signal routing capabilities, the CLB can replicate many common functions typically assigned to external programmable logic ICs. Unlike CPLDs or FPGAs, which often require dedicated programming tools and complex development environments, the CLB is configured entirely through standard MPLAB tools, streamlining integration and reducing development overhead. This makes it particularly attractive for embedded applications where space, cost, and power efficiency are critical, and where modest custom logic can be embedded directly within the microcontroller itself.

The PIC16F13145 microcontroller includes 32 Look-Up Tables (LUTs) within its CLB module, offering ample resources to implement a 6-bit BRM. This makes it well-suited to projects requiring either multi-output mid-resolution control or single-output high-resolution frequency scaling. Since the CLB Synthesizer supports logic gates with a maximum of four inputs, implementing more complex logic, such as the 6-bit equality comparator, requires cascading multiple smaller gates. To support reusability and maintain clarity, the BRM logic for an individual output channel is encapsulated into an Off-Sheet CLB module. This modular design approach allows multiple BRM output channels—each with their own configurable N values, to be instantiated and managed within the Main CLB module, offering a scalable solution for parallel and independent frequency outputs.

Each BRM output channel’s N value—the binary control word that defines its output frequency—is configured by writing to the CLB Software Input register (CLBSWIN). This register allows direct software control over the internal CLB logic, enabling the firmware to “bit-bang” 6-bit value, depending on the resolution of the BRM, into the appropriate LUTs for each channel. This real-time configurability means that the output frequency can be adjusted dynamically without the need to modify or recompile the underlying logic design. Each BRM channel generates its own CLKOUT signal, and a shared SYNCOUT signal is also produced as a timing reference, typically aligned with the start of the counter cycle. These signals are routed through the CLB’s output steering logic to assigned GPIO pins, making them accessible for external circuitry in applications such as motor control, digital communications, and clock domain interfacing.

In addition to utilizing CLB1 for implementing the Binary Rate Multiplier (BRM), several other on-chip peripherals of the PIC microcontroller are also employed to support internal clock generation and frequency measurement.

PWM1 and Timer2 (TMR2) are configured to produce an internal clock signal, routed to the INT-CLKOUT output. This signal serves as a controlled and tunable input frequency for testing the BRM logic without relying on external clock sources. The frequency of this internal clock is managed through a read/write variable named BRM_IntClockFrequency, allowing it to be adjusted dynamically during runtime or through a development interface.

To measure the frequency of an external input at CLKIN, a gated timing method is implemented using Timer0 (TMR0) and Timer1 (TMR1). These timers work together to sample the number of input pulses over a fixed time window, resulting in a measured input frequency stored in the read-only variable BRM_InputFrequency. This provides real-time visibility into the clock signal feeding the BRM.

The fractional divisor N, which determines the ratio of CLKINto CLKOUT (i.e., N/16 or N/64), is stored in the read/write variable BRM_DivisionNumber. This value is used by the firmware to program the CLB logic accordingly. The resulting divided frequency is calculated and presented as the read-only variable BRM_OutputFrequency, giving users a complete view of the BRM’s current configuration and performance.

To monitor and interact with the BRM implementation in real time, the MPLAB Data Visualizer was used in conjunction with the Data Visualizer Runtime (DVRT) protocol. This configuration enabled seamless communication between the microcontroller and the development environment, allowing both visualization and modification of key program variables. The DVRT Dashboard was employed to display real-time data such as the input clock frequency, output frequency, and the current N values for each BRM channel, providing clear insight into system behaviour. In parallel, the DVRT Streaming Table was used to dynamically adjust the N values, sending updates directly to the firmware without interrupting program execution. This approach facilitated efficient testing, calibration, and debugging by offering a responsive, non-intrusive interface for real-time control and monitoring of the BRM parameters.

For the purpose of creating a rudimentary BRM, the schematic diagram has been kept minimal, as the PIC16F13145 Curiosity Nano board provides all the necessary connectivity for rapid prototyping. While signal conditioning circuitry could be added for protection, it was deemed unnecessary for the scope of this article.

This diagram presents the overall structure of the 6-bit BRM as configured in the MPLAB Code Configurator (MCC) CLB Synthesizer. It shows how the Off-Sheet BRM module is instantiated within the main CLB project, including signal routing for the input clock (CLKIN), the BRM output (CLKOUT), and the synchronizing pulse (SYNCOUT). This hierarchical high-level view highlights the modular design and how multiple BRM channels can be managed in parallel.

This image illustrates the internal logic of the 6-bit BRM, detailing how LUTs and basic gates are used to implement the gating mechanism. The logic compares the 6-bit counter output to the software-defined N value, enabling CLKOUT only on matching counts. Due to the 4-input limit of the CLB gates, some logic expressions are broken down into cascaded gates.

Here, the synchronous 6-bit binary counter is shown, built using JK flip-flops and supporting logic. It divides the input clock into 64 sequential phases (CLKIN/2, CLKIN/4, etc.), which are used as timing references for the BRM logic. The design ensures minimal propagation delay and consistent timing across all outputs.

The DVRT Streaming Table interface for the 6-bit BRM shows how users can enter N values in the range of 1 to 63. This table directly feeds into the CLBSWIN register, allowing real-time changes to the BRM configuration without halting execution, critical for testing and tuning in dynamic environments.

In this view, the DVRT Dashboard presents live feedback on the 6-bit BRM’s operation, including input frequency, calculated output frequency, and current N values. The dashboard provides essential insight for confirming the accuracy of the logic and verifying that the BRM responds appropriately to updated control values.

This oscilloscope capture provides a visual confirmation of the 6-bit BRM’s operation. The CLKOUT waveform reflects the output frequency determined by the current N = 13 setting, while the SYNCOUT pulse marks the start of each 64-count cycle. The captured signals verify proper timing, synchronization, and output behaviour.

This screenshot illustrates the functionality of a single-channel 6-bit BRM, again evaluated using the Digilent Analog Discovery device and the WaveForms software suite. A 5 MHz input clock generated by the WaveForms pattern generator is connected to the BRM’s CLKINinput. The WaveForms Logic Analyzer captures the resulting CLKIN, SYNCOUT, and CLKOUT signals. For this example, the BRM is configured with N = 13, resulting in an output frequency of 13/64 × 5 MHz = 1.015625 MHz.

The SYNCOUT signal appears once every 64 clock cycles, indicating the start of each counting sequence. The CLKOUT waveform shows 13 gated pulses per 64-cycle window, accurately reflecting the expected output based on the programmed N value. This example highlights the precision and flexibility of the 6-bit BRM implementation, demonstrating fine-grained frequency division using the CLB and real-time verification with the Analog Discovery and WaveForms tools.

Having a reliable method for dividing an input frequency by a fractional integer ratio is highly valuable in modern digital systems. Such capability is essential in applications including digital waveform synthesis, pulse-width modulation, software-defined radio, clock generation for communication protocols, and timing control in embedded systems.

Both the dual-channel 4-bit BRM and the single-channel 6-bit BRM perform remarkably well, even when assembled on a breadboard using standard 'flying jumper leads'. When operated on the Curiosity Nano board, reliable functionality is maintained with CLKIN frequencies up to approximately 10 MHz. For higher operating frequencies, performance can be further improved by designing a custom PCB with careful attention to signal integrity, specifically minimizing path inductance and parasitic capacitance through proper trace layout, grounding, and decoupling techniques.

Once the CLB bitstream has been loaded typically during initialization after reset, the microcontroller can be placed into Sleep mode, allowing the BRM to continue operating independently. Since the Configurable Logic Block (CLB) functions autonomously, the BRM remains fully active without requiring further MCU intervention, enabling continued operation even while the PIC microcontroller is in a low-power state. This makes the design particularly well-suited for energy-efficient or battery-powered applications.

74LS97
CD4089