A stable 10MHz sine-wave frequency reference for phase locking to a 1MHz GPS disciplined oscillator

Written by Guy Fernando

Created Oct 2021 - Last modified Sep 2024

A standard atomic frequency reference is typically a Cesium or Rubidium clock, accurate to 1 second in 300 years.
A precision frequency reference is a very useful piece of test equipment as a calibration standard, but is often beyond
the reach of the average hobbyist. Since GPS satellites actually use onboard Cesium and Rubidium atomic clocks as
their timing source, the next best thing and a far cheaper option is to use a GPS receiver as a timing source. Receiver
modules known as a GPS disciplined oscillators (GPSDO) are widely available and many are designed to provide a low
jitter phase coherent signal known as a ‘time-pulse’.

GPSDO modules can be configured to output a wide range of time-pulse frequencies owing to their internal Fractional N
Synthesizer. However a low jitter signal is only realized when the output frequency is a factor of the module’s clock
frequency. For example the U-Blox NEO-M8P module uses a 48MHz master clock, so the time-pulse output is jitter free only
when generating frequencies of 12MHz, 8MHz, 6MHz, 4MHz, 2MHz, or 1MHz etc. Unfortunately the 10MHz frequency is absent
from the list. A reference frequency of 10MHz is especially important since it is often used for calibration purposes,
or as a timing clock for controlling other test instruments.

To overcome this problem the design discussed here uses a standard Phase Locked Loop (PLL) approach consisting of a
÷10 digital divider, a phase frequency detector and an adjustable 10MHz Oven Controlled Crystal Oscillator (OCXO), to
phase lock the 10MHz output from the OCXO to the precision 1MHz time-pulse signal from the GPSDO.

As already mentioned the circuit is a standard design. The PLL, when operating within its operating range, will
acquire and lock to the input signal, track it in frequency, and exhibit a fixed phase relationship relative to the
input. The MC4044 chip contains two phase detectors, a charge pump and an amplifier. Detector #1 is a phase and
frequency detector whose output is connected to the charge pump. This serves two purposes; to generate an error
voltage proportional to the phase or frequency difference and in conjunction with the amplifier to serve as the loop
filter. Detector #2 a simple exclusive-or phase detector which is able to acquire a quadrature lock and is used to
indicate an out of lock (slip indicator) condition.

The loop filter components are chosen to set the loop bandwidth, capture time and transient response, and are
primarily characterized by R1, R2 and C1. Q1 is connected as an emitter follower and is used to buffer the
amplifier, this allows for R1 to be increased when a lower phase detector gain stage is required. The error signal
from the amplifier output is fed into the OSC5A2B02 OCXO Vref pin to trim the 10MHz square wave output frequency. This
output square wave is fed into the 74HC4017 decade counter which divides the 10MHz output frequency down for
comparison by the phase detector, thus closing the control loop.

Two 10MHz outputs are available; one TTL square wave and one sine wave. It was found that a basic 2nd order Chebyshev
low-pass filter consisting of L1 and C6 was sufficient enough to reduce unwanted harmonic content. However a higher order
filter could be devised, if a cleaner signal output is desired.

Switch SW1A is used to bypass the output from the loop filter and use an internal fixed voltage reference set by RV1.
This allows the device to be used when no GPSDO input signal is available, and just a ‘near’ 10MHz frequency reference
is required.

The circuit is powered by an external 12V DC supply which is dropped by the LM7805 voltage regulator down to 5v suitable
for powering the OCXO and the integrated circuits. A power source capable of supplying at least 500mA is required since
the oven part of the OCXO can draw near to this current when cold.

The Motorola MC4044 datasheet describes with equations detailing how to calculate loop filter component values, R1, R2
and C1 for various circuit cases. For the circuit discussed in this article, the input parameters are listed below and
form the dependencies for the calculated loop filter component values. For R1 the datasheet recommends a value of 1kΩ,
the other resultant values, R2 and C1 are calculated below using the equations found in the datasheet.

\( \begin{aligned}
Resistor, R1 = 1 \text{ } k \Omega
\end{aligned} \)

\( \begin{aligned}
Reference \text{ } Frequency, f_{ref} = 1 \text{ } MHz
\end{aligned} \)

\( \begin{aligned}
OCXO \text{ } Min \text{ } Frequency, f_{min} = 9.99992 \text{ } MHz
\end{aligned} \)

\( \begin{aligned}
OCXO \text{ } Max \text{ } Frequency, f_{min} = 10.00008 \text{ } MHz
\end{aligned} \)

\( \begin{aligned}
OCXO \text{ } Output \text{ } Frequency, f_{out} = 10 \text{ } MHz
\end{aligned} \)

\( \begin{aligned}
OCXO \text{ } Voltage \text{ } Range, V = 5 \text{ } V
\end{aligned} \)

\( \begin{aligned}
Required \text{ } Lock \text{ } Time, t = 50 \text{ } ms
\end{aligned} \)

\( \begin{aligned}
Required \text{ } Damping \text{ } Factor, \zeta = 0.05
\end{aligned} \)

\( \begin{aligned}
Required \text{ } Settling \text{ } Cycles, \omega_nt = 4.5 \text{ } rads
\end{aligned} \)

\( \begin{aligned}
Phase \text{ } Detector \text{ } Gain \text{ } (where \text{ } R1 = 1k\Omega), K_{\phi} = 0.1
\end{aligned} \)

\( \begin{aligned}
Division \text{ } Factor, N = \frac{ f_{out} }{ f_{ref}} = \frac{ 10 }{ 1} = 10
\end{aligned} \)

\( \begin{aligned}
VCO \text{ } Gain, K_v = \frac{ 2\pi( f_{max} - f_{min} ) }{ V } = \frac{ 2\pi.160 }{ 5} = 201 \text{ } rads/s/V
\end{aligned} \)

\( \begin{aligned}
Settling \text{ } Time \text{ } Constant, \omega_n = \frac{ \omega_nt }{ t } = \frac{ 4.5 }{ 0.05} = 90 \text{ } rads/s
\end{aligned} \)

\( \begin{aligned}
Capacitor, C1 = \frac{ K_{\phi} . K_v }{ N . \omega_n^2 . R1 } = \frac{ 0.1 . 201 }{ 10 . 90^2 . 1000} = 0.248 \text{ } \mu F
\end{aligned} \)

\( \begin{aligned}
Resistor, R2 = \frac{ 2\zeta }{ \omega_n . C1 } = \frac{ 2 . 0.05 }{ 90 . 2.482E-007} = 4.476 \text{ } k \Omega
\end{aligned} \)

The closest preferred component values for R2 and C1 are 4.7kΩ and 0.22µF respectively.

The 10MHz time-pulse signal derived straight from the U-Blox M8P GPSDO is unusable in many cases due to the excessive
phase noise or jitter generated at this frequency. The circuit discussed here overcomes the problem and performs
admirably even when constructed on stripboard.

Motorola MC4044 Datasheet

Phase Locked Loop

GPS Disciplined Oscillator

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